BaseJump Manycore

Welcome to BaseJump Manycore.

Brought to you by Taylor's Bespoke Silicon Group.

Code

See bsg_manycore GitHub git repo.

BaseJump Manycore makes use of BaseJump STL, and
BaseJump FPGA Bridge as well.

See our Quickstart guide for using Celerity, the open source 511-core chip. The Celerity tapeout was funded by the DARPA CRAFT program.

Since then, we have been a part of the DARPA SDH program and have been improving the architecture to make it more programmable using a CUDA-like language. The latest version is called HammerBlade Manycore. See bsg_manycore GitHub git repo for the latest code and documentation. A 14- nm prototype was taped out in August 2019. It is a ridiculously awesome chip.

Publications

See these publications for more details:

Evaluating Celerity: A 16nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizeable PLL. Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski. In IEEE Solid State Circuits Letters, December 2019. (pdf) (bib)
A 1.4 GHz 695 Giga RISC-V Inst/s 496-core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. B. Taylor and R. G. Dreslinski. In Symposium on VLSI Circuits, June 2019. (pdf)
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric.
by Scott Davidson, Shaolin Xie, Chris Torng, Khalid Al-Hawaj, Austin Rovinski, Tuto Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald Dreslinski, Christopher Batten, Michael Bedford Taylor.
IEEE Micro, March/April 2018. (pdf)(bib)
Celerity: An Open Source RISC-V Tiered Accelerator Fabric.
This is an overview of our Tiered Accelerator Fabric architecture, and of a 511-core RISC-V implementation in 16 nm, including 5 Linux-capable RISC-V cores, 496-core RISC-V manycore, and a binarized neural network. (Our team, the Bespoke Silicon Group did the architectural design, with the exception of the neural network, which was done by Cornell.)
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael Bedford Taylor and Zhiru Zhang.
Proceedings of Hotchips, 2017. (pdf)(bib)
Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm.
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Rajesh K. Gupta, Michael Bedford Taylor and Zhiru Zhang.
Has more details on the open source code for Celerity.
Proceedings of CARRV, October 2017. (pdf)
The BaseJump Manycore Accelerator Network. Shaolin Xie and Michael Bedford Taylor. Published on arxiv.org. August 1, 2018.

Contact prof.taylor@gmail.com for more details.

We are looking for collaborators who are excited about developing programming methodologies for and using manycore chips.

e.g., Remote Store Programming, Streaming, CUDA, OpenCL, Halide, OpenSHMEM...

Email prof.taylor@gmail.com

496-core BaseJump Manycore (@ 1.4 GHz) in Celerity Chip (16nm TSMC FinFet technology)

BaseJump Manycore has been combined and used in the 511 RISC-V Core Open Source Celerity
chip which was taped out in TSMC 16nm FinFet technology in April 2017.

The pictures below are the chip layout, the architectural diagram, and the 16nm silicon:

Click here for a super high-res layout of the chip.

Celerity couples the 1.4 GHz 496-core BaseJump Manycore array to 5 Rocket cores via independent RoCC links. It also has a neural network accelerator with multiple connections to the manycore. The manycore can do stores that traverse across the mesh and write directly into the neural network state. The daughterboard in the picture below is the Celerity system running. The Zedboard on the right provides DRAM and ethernet connectivity.

On the same chip, there is also a 10-core version of the manycore in a low-voltage domain, which was first prototyped below in Dec 2016:

10-core RISC-V BaseJump Manycore in "BSG Ten" ASIC (180 nm TSMC)

Taylor BSG teammembers (Scott Davidson, Chun Zhao, Shaolin Xie and Michael Taylor) have also taped out a 10-core manycore in TSMC 180 (commit_tag).

This chip multiplexes the the south side of the manycore directly to the off-chip I/O interface using the T block. An FPGA can be used to extend the manycore in the south direction, or alternatively you can couple the manycore to a processor inside an FPGA.

Connectivity looks like this:

Connectivity
Tile 0	Tile 1
Tile 2	Tile 3
Tile 4	Tile 5
Tile 6	Tile 7
Tile 8	Tile 9
T
/	\
A
/ / / \| \| \ \ \
I O I O I O I O

Key:

Label	Block
0-9	RISC-V Cores 0..9
I	8-bit High-Speed Source Synchronous Input DDR channel
O	8-bit High-Speed Source Synchronous Output DDR channel
C	Clock generator
A	Assembler (combines 4 8-bit channels into wide 32-bit channel)
T	Tunnels two southern most network links as independent logical channels to off-chip FPGA
/	Cross-chip channels

(Click on the pictures for larger view.)

Click here for zoomed-in photos of the chip.

Shmoo plot confirming operation at 280 MHz @ 1.8V and 370 MHz @ 2.4V

Our High-Speed Singled-Ended DDR I/O (using off-the-shelf 3.3V TTL) has been confirmed to work at ~390 MHz with 16mA outputs.

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